An integrated circuit typically includes an internal power grid for distributing power to its various internal cores or other internal subsystems and components. During testing of the integrated circuit, the power grid may be analyzed under various parameter settings and other expected operating conditions in order to ensure that sufficient voltage is provided for the integrated circuit to function properly over all of those operating conditions. This process often involves utilization of so-called IR drop analysis techniques implemented using automated test equipment. For example, these techniques may be used to determine voltage drop of a primary supply voltage such as Vdd for particular operating speeds of the integrated circuit. The IR drop analysis in this example may involve repeating the measurements not only over the multiple operating speeds, but also over other operating conditions, such as at different temperatures and supply voltage levels.
A significant drawback of conventional practice is that results of the above-described IR drop analysis based on measurements from automated test equipment are not readily predictable or otherwise verifiable using integrated circuit design software. This can in some cases be attributable to the particular arrangement of automated test equipment that is being used to collect the IR drop measurements, and in other cases may be due to inaccuracies in the integrated circuit design software.
In any event, this inability to correlate actual IR drop measurements with predicted design values can contribute to undesirable situations in which integrated circuits have power grids that are over-designed for the expected operating conditions, possibly leading to excessive manufacturing costs, or alternatively have power grids that provide insufficient design margin over the operating conditions.
The above-described conventional approaches become even more problematic as device dimensions continue to shrink with advances in integrated circuit process technologies. This is because such shrinking device dimensions tend to coincide with increasingly larger power densities, lower supply voltages and higher operating speeds in the corresponding integrated circuits, thereby further complicating design verification.